The present invention relates to a method of and apparatus for generating timing information from a bit stream transmitted in a communications network, the bit stream being of the type having a constant bit rate.
Asynchronous Transmission Mode (ATM) communication networks are packet-based networks capable of permitting communication of information between a source network entity and a destination network entity. Due to the packet nature of ATM, network resources can be shared between many users. Additionally, ATM networks can support multiplexing of a number of services, for example, voice, data or images. Typically, the source network entity transmits cells of information to the destination network entity, the destination network entity comprising a destination clock coupled to a destination buffer.
A service supported by the ATM network, for example video, can require the source network entity to receive a bit stream having a constant bit rate for transmission to the destination network entity. In such cases, proper delivery of traffic relating to the service depends upon the destination clock controlling the destination buffer being in synchronism with the frequency of the bit stream received by the source network entity. If the destination clock is not in synchronism with the bit stream received by the source network entity, information is usually lost as a result of buffer over- or under-flow. Consequently, it is necessary to generate timing information specific to the service being supported by the ATM network.
U.S. Pat. No. 5,260,978 discloses a technique for generating and transferring timing information over asynchronous communication channels by encoding a measurement of a phase of an incoming, constant bit rate, signal relative to a single master, or network, clock. The measurement of the phase, known as a synchronous Residual Time Stamp (SRTS), comprises counting a number, n, of clock cycles (of a derived network clock) having a frequency of fnx within a gating period determined by a number, N, of clock cycles of the incoming signal (having a frequency fs) corresponding to the service. Hence, a representation (the encoded measurement) of the number of network clock cycles within a defined window surrounding an expected, or nominal, number of signal clock cycles is transmitted from the source network entity to the destination network entity using a reserved space in cell headers.
A timestamp is sampled every Tm period. The following equation yields a number of cycles, n, of the network-derived clock at the frequency fnx in the N cycles of the incoming signal having the frequency of fs:
n=N.Y/(X+"PHgr")xe2x80x83xe2x80x83(1)
Where:
X is the number cycles of the plesiochronous bits, at a nominal frequency fs,
Y is a number of cycles of the network-derived clock signal running at a frequency of fnx, and
"PHgr" is a phase offset, in cycles, between the plesiochronous bit stream and the network-derived clock after the period Tm.
However, in the case of the SRTS (an ongoing count) loss of quantisation errors, and hence information, must be avoided because n constitutes the timestamp. Therefore, the SRTS is added to any previous SRTS for every timestamp period, any errors being maintained and added back in when they constitute a whole cycle (timestamp quantum).
At the destination network entity, upon receipt of the encoded measurement, the destination clock uses the encoded measurement and the signal from the network clock to reconstruct the clock cycles of the incoming signal.
It can be seen that the above described phase measurement technique requires the incoming signal. However, service signals received by the source network entity can be multiplexed within a plesiochronous frame or mapped within a synchronous container of a Synchronous Optical NETwork (SONET)/Synchronous Digital Hierarchy (SDH) frame, or both. Consequently, it may not be necessary to regenerate an incoming signal of interest before onward transmission or it may not be possible to access the service clock frequency fs. Alternatively, access to the incoming signal may only be possible by first demapping or demultiplexing the incoming signal of interest; demapping or demultiplexing of the incoming signal is undesirable, because delays are introduced and system complexity is increased.
According to a first aspect of the present invention, there is provided a method of generating timing information from a stream of bits, the method comprising the steps of: receiving a master clock signal; receiving the stream of bits; identifying and counting justification events in the stream of bits over a predetermined number of bits in the stream of bits, and generating timing information in response to the count of justification events and the master clock signal.
Preferably, the stream of bits comprises a plurality of multiplexed signals corresponding to a respective plurality of services.
Preferably, the above method further comprises generating the timing information using the following equation: n=N.Y/(X+Jxe2x88x92U), where: n is the timing information, N is the predetermined number of bits in the stream of bits, X is a number of cycles of containers holding the stream of bits over the predetermined number of bits in the stream of bits, Y is a number of cycles of the network clock, and J is a number of justification events and U is a number of used justification opportunities at nominal frequency of the stream of bits.
Preferably, the above method further comprises forming an SRTS value from a plurality of Least Significant Bits (LSBs) from the timing information. More preferably the plurality of LSBs is four LSBs.
Preferably, the above method further comprises feeding back timing information.
According to a second aspect of the present invention, there is provided a timing information generation apparatus comprising: a first input for receiving a master clock signal; a second input for receiving a stream of bits; means for identifying and counting justification events in the stream of bits over a predetermined number of bits in the stream of bits; means for generating timing information in response to the count of justification events and the master clock signal.
Preferably, the stream of bits comprises a plurality of multiplexed signals corresponding to a respective plurality of services.
Preferably, the means for generating timing information uses the following equation: n=N.Y/(X+Jxe2x88x92U), where: n is the timing information, N is the predetermined number of bits in the stream of bits, X is a number of cycles of containers holding the stream of bits over the predetermined number of bits in the stream of bits, Y is a number of cycles of the network clock, J is a number of justification events and U is a number of used justification opportunities at a nominal frequency of the stream of bits.
Preferably, the timing generation apparatus further comprises means for forming an SRTS value from a plurality of Least Significant Bits (LSBs) from the timing information. More preferably, the plurality of LSBs is four LSBs.
According to a third aspect of the invention, there is provided a method of generation of justification events comprising the steps of: obtaining timing information from a received stream of bits; generating an initial at least one justification event; generating internal timing information in response to the initial at least one justification event; controlling the generation of subsequent justification events in response to any discrepancy between the received timing information and the internally generated timing information.
Preferably, the above method further comprises controlling the generation of subsequent justification events with a PID controller.
Preferably, any discrepancy between the received timing information and the internally generated timing information is determined using a subtractor.
According to a fourth aspect of the present invention, there is provided a justification event generation apparatus comprising: an input for receiving a stream of bits containing source timing information; means for generating an initial at least one justification event; means for generating internal timing information in response to the initial at least one justification event; controller means for the generating subsequent justification events in response to any discrepancy between the source timing information and the internally generated timing information.
Preferably, the controller means is a PID controller.
Preferably, there is provided a subtractor arranged to determine any discrepancy between the source timing information and the internally generated timing information.
According to a fifth aspect of the present invention, there is provided a communication system comprising a source network entity capable of communicating with a destination network entity via a communication network, the source network entity including a timing information generation apparatus comprising: a first input for receiving a master clock signal; a second input for receiving a stream of bits; means for identifying and counting justification events in the stream of bits over a predetermined number of bits in the stream of bits; means for generating timing information in response to the count of justification events and the master clock signal.
According to a sixth aspect of the present invention, there is provided a communication system comprising a source network entity capable of communicating with a destination network entity via a communication network, the destination network entity including justification event generation apparatus comprising: an input for receiving a stream of bits containing source timing information; means for generating an initial at least one justification event; means for generating internal timing information in response to the initial at least one justification event; controller means for the generating subsequent justification events in response to any discrepancy between the source timing information and the internally generated timing information.
According to a seventh aspect of the present invention, there is provided a computer program element comprising computer program code means to make a computer execute the method of generating timing information set forth above.
Preferably, there is provided a computer program element as set forth above in relation to the generation of timing information embodied on or in a computer readable medium.
According to an eighth aspect of the present invention, there is provided a computer program element comprising computer program code means to make a computer execute the method of generating justification events set forth above.
Preferably, there is provided a computer program element as set forth above in relation to generation of justification events embodied on or in a computer readable medium.
According to a ninth aspect of the invention, there is provided a use for a plurality of justification events in a stream of bits, wherein the plurality of justification events are counted relative to a master clock signal during a predetermined period, the counted justification events corresponding to timing information of the stream of bits.
According to a tenth aspect of the present invention, there is provided computer executable software code stored on a computer readable medium, the code being for generating timing information from a stream of bits, the code comprising: code to receive a master clock signal; code to receive the stream of bits; code to identify and count justification events in the stream of bits over a predetermined number of bits in the stream of bits, and code to generate timing information in response to the count of justification events and the master clock signal.
According to an eleventh aspect of the present invention, there is provided a programmed computer for generating a timing information from a stream of bits, comprising memory having at least one region for storing computer executable program code, and a processor for executing the program code stored in memory, wherein the program code includes: code to receive a master clock signal; code to receive the stream of bits; code to identify and countjustification events in the stream of bits over a predetermined number of bits in the stream of bits, and code to generate timing information in response to the count of justification events and the master clock signal.
According to a twelfth aspect of the present invention, there is provided a computer readable medium having computer executable software code stored thereon, the code being for generating timing information from a stream of bits and comprising: code to receive a master clock signal; code to receive the stream of bits; code to identify and count justification events in the stream of bits over a predetermined number of bits in the stream of bits, and code to generate timing information in response to the count of justification events and the master clock signal.
According to a thirteenth aspect of the present invention, there is provided a computer executable software code stored on a computer readable medium, the code being for generating justification events, the code comprising: code to obtain timing information from a received stream of bits; code to generate an initial at least one justification event; code to generate internal timing information in response to the initial at least one justification event; code to control the generation of subsequent justification events in response to any discrepancy between the received timing information and the internally generated timing information.
According to a fourteenth aspect of the present invention, there is provided a programmed computer for generating justification events, comprising memory having at least one region for storing computer executable program code, and a processor for executing the program code stored in memory, wherein the program code includes: code to obtain timing information from a received stream of bits; code to generate an initial at least one justification event; code to generate internal timing information in response to the initial at least one justification event; code to control the generation of subsequent justification events in response to any discrepancy between the received timing information and the internally generated timing information.
According to a fifteenth aspect of the present invention, there is provided a computer readable medium having computer executable software code stored thereon, the code being for generating justification events and comprising: code to obtain timing information from a received stream of bits; code to generate an initial at least one justification event; code to generate internal timing information in response to the initial at least one justification event; code to control the generation of subsequent justification events in response to any discrepancy between the received timing information and the internally generated timing information.
It is thus possible to provide a method of and apparatus for generating timing information for use in a packet based network without the need to demultiplex or demap incoming signals. The timing information can be derived without direct counting of the number of clock cycles of the incoming signal or direct generation of the derived network clock. Furthermore, the present invention is suitable for algorithmic execution and is capable of interworking with existing SRTS implementations. Consequently, the present invention is simpler and cheaper to implement.